Vector Network Analyzer (Power Supply)
Overview
I want to have this whole board powered from a 12 volt wall wart. This switcher will take the 12 volts and produce 2 rails: 3.8 volts and 2.3 volts. These rails will then be used to produce 3.3V, 1.8V, and 1.2 volt rails using linear regulators. The linear regulators will be sequenced using the MAX16042 power supervisor IC. The VCCIOX rails will be powered on first, the VCCAUX rail will be powered on second, and the VCC rail will be powered on third. This accommodates the FPGA recommended power up sequence.
I want to have this whole board powered from a 12 volt wall wart. This switcher will take the 12 volts and produce 2 rails: 3.8 volts and 2.3 volts. These rails will then be used to produce 3.3V, 1.8V, and 1.2 volt rails using linear regulators. The linear regulators will be sequenced using the MAX16042 power supervisor IC. The VCCIOX rails will be powered on first, the VCCAUX rail will be powered on second, and the VCC rail will be powered on third. This accomodates the FPGA recommended power up sequence.
We will probably have two sets of these switcher / linear regulator combos, only differing in that one will have EMI filtering on the input to the switcher. The supply with EMI filtering will be used to power the analog supplies of the important components: PLL chips, ADC, RF filters, and RF switches.
Power Requirements
To determine how beefy of a power supply I needed to design, I drew a map of all the components I wanted to power and jotted down the max current draw from each rail from each component. This let me size up my power supply. Most peripherals to the FPGA operated at 3.3V. The ethernet controller required two other rails, but it provided its own internal linear regulators for those rails. So the auxiliary power for the FPGA as well as most VCCIOX supplies will run at 3.3V. The ADC digital communication lines run at 1.8V, so we need a 1.8V supply for the ADC digital rail as well as for the corresponding VCCIOX supply pin on the FPGA. The core of the FPGA operates at 1.2V, so we need a 1.2V rail to accommodate that.
I decided that I wanted to use a switching converter followed by a few LDO's to generate the power supplies for these components. Which means I can use the switching converter to generate 3.8V and then use a linear regulator to step it down to 3.3V. I can use the second output on the switching converter to produce 2.3V, and use two separate linear regulators to step it down to 1.8V and 1.2V.
Using the plot on the right and a whole lot of rounding up, I determined that the max current I expected to be pulled from the 3.8V rail was about 750 mA, and the max current I expected to be pulled from the 2.3V rail was about 425 mA. So, I designed my switcher to be capable of supplying 3A per rail.
LTC3633 Simulations
I designed the power supply in LTSpice. I added some hefty soft-start. I also picked inductors that were bigger than are needed for a 2MHz switcher, but I really want my ripple current low because I want a monotonic ramp on startup and don't want to deal with any funny business caused by the switcher dropping out of CCM. I also sequenced the start up of the two rails using the PG lines on this switcher. Turns out the sequence order isn't going to matter much, and neither will the monotonic behavior of the ramp, because I am going to wait till these rails are fully up, then I will turn on LDO's in sequence that power the FPGA and peripherals.
Below are the images of the simulation results as well as the math I went through to pick the inductor and capacitors. In the results, notice that the startup is linear and perfectly monotonic, changes in the input voltage don't even seem to affect the output voltage, and the output voltage only deviates about 3mV from its nominal value and returns in a critically damped fashion under maximal load changes.
Linear Regulators
I then added 3 linear regulators in the ADP7158 family of parts. They offer high PSRR and are intended for doing funky stuff like powering PLL's. I know this is the power supply for the digital portion of the board, but I'll probably copy this power supply over for the RF side and just add some EMI filters. Also, less noise = more better, so since I already put enough money into this project, I am just using this as an expensive excuse to technically flex.
To the right, you can see the schematic for one of these three linear regulators. They all have identical schematics with slightly different part numbers.
Power Sequencer
I used a MAX16042 power supervisor chip to handle the startup sequence of these power supplies, with the ramps of the 3 different rails starting 13ms apart. The reset line for the whole system is also managed by this chip. The reset will be released 220 ms after the last rail goes high.
The sequence of the rails is as follows. First the 1.8V rail goes high since that powers a VCCIO bank on the FPGA. Then the 3.3V rail goes high since that powers the other VCCIO rails on the FPGA (as well as auxiliary power). Lastly, the 1.2V rail powering the FPGA core goes high.
To the right, you can see the schematic for this power sequencer.
