Vector Network Analyzer (RF Design)

Overview

Yes, the cover photo for this project is just a smith chart. I'll replace it with something more relevant once I capture my own S parameter measurements.

Let's get to it.

For this project, the major components we will need are: something to synthesize the RF over our wide band, a receiver that operates over that wide band to extract our I and Q data, an FPGA to process the sampled data.

For our RF synthesizer, I am choosing to use a fractional PLL chip made by analog devices for a few reasons. 1 COST!!! For $90 bucks I can get a chip that generates 53.125 MHz to 13.6 GHz. There are quite a few wideband PLL chips, but few have integrated VCO's. And to make use of the wideband that many PLL chips claim to support, you'd need your own external bank of VCO's. That would quickly complicate the design. The ADF5356 has an integrated bank of VCO's, so that chip is our choice.

For our RF receiver, we want as low a noise figure as possible so we don't degrade our SNR and impede our ability to measure small power levels, and we want highly linear components - or as few non-linear things as we can get away with. We don't want to be introducing any intermodulation products in the receive chain of this device. The VNA would be useless if features in the RF measurements were influenced by the measurement equipment. So for our receive chain, we'd like to stick to a LNA right up front (gain before anything else helps keep the noise figure low in a cascade of components) followed by a mixer to an intermediate frequency that we sample.

Theoretically we could mix right down to baseband (direct conversion) and use our single RF synthesizer as the LO to mix itself back down, but we'd run into a tough problem. We want to capture IQ data for phase, so we'd need a 90 degree phase shifter that operated over that ultra-wideband (50 MHz to 13.6 GHz). That complication makes this method prohibitively expensive. Phase shifters this wideband typically cost between $500 and $1000 dollars. Another problem with direct conversion in general is that the LO tends to couple into the RF port of the mixer and produces an erroneous DC output. Instead we are going to run two identical RF synthesizers on this board with a fixed offset frequency. This will allow us to mix down to a fixed IF frequency, sample, and digitally mix to baseband in the FPGA with a sin/cos lookup table.

I want a maximum IF bandwidth of 100 MHz so we don't have to wait forever for this thing to sweep from its low to high measurement frequency. So I will shoot to set the IF frequency at 50 MHz. The upper edge of the IF band is at 100 MHz, so we will want a 200MHz sample rate. I have chosen the MCP37231 16 bit ADC as our analog to digital converter.

Later in this design, we will need to design our own directional couplers. I think I am going to use this as an opportunity to learn openEMS since it is free, and CST and HFSS are prohibitively expensive for individuals.

I believe that sums up the overview of the RF portions of this board. Obviously we will need many power rails, a means to communicate with this board, and a few other things. Those will be discussed when it is time to draw up the schematic.

RF Synthesizer

Aright, before we get into the block diagrams, lets talk about our big concern with the fractional PLL synthesizer as this will drive most of our design around this part. SPURS. We are trying to make a piece of test equipment to measure behavior of a DUT including any non-linear intermodulation products it produces. That is going to be tough if our device is throwing our spurs at all different frequencies. You may say, well, cant we push the spurs outside our IF bandwidth or calibrate them out? The answer is we will do some of that for sure, but we want as close to a single tone coming out of this synthesizer as possible. Consider that a spur produced falls outside the IF bandwidth of the device. A non-linear device could "mix" some of that energy back into our band and cause erroneous measurements. Listed below are the spurs we will have to deal with and our chosen method of dealing with them.

Reference Spurs:

These spurs occur at multiples of the PLL reference frequency away from the fundamental. These are still too close to the fundamental to filter them out at the higher frequencies, but not all hope is lost. For one, these spurs aren't huge. The data sheet lists "Spurious Signals Due to PFD Frequency" as typically being 85 dB below the fundamental. I'm tempted to not worry, but there is one other thing we can do to mitigate these spurs and their impact on our measurements. If we can set the reference frequency of our fractional PLL chip above our max IF bandwidth frequency, then we can push all of these spurs completely out of our band of interest. Furthermore, the only way these spurs could make it back into our band is if they mix on a non-linear DUT (or our receiver) causing intermodulation products to show up in our band of interest. These will be smaller than the spurs themselves by a solid margin, and the reference spurs were already at -85 dBc. So by setting our PLL reference frequency above our max IF bandwidth frequency, we can mitigate the problems caused by these spurs.

Integer-N Boundary Spurs:

These spurs begin to pop up as we move our VCO / RF output close to an integer multiple of the reference frequency. These spurs are generally larger in magnitude than the fractional spurs or reference spurs and tend to cause problems. Due to the nature of them showing up only as we approach certain frequencies, these tend to be located close to the fundamental / frequency of interest and are hard to filter out. Fortunately, we can just adjust our reference frequency (and adjust our fractional-N and integer-N PLL terms accordingly) so that we generate the same output frequency without it being at an integer multiple of the reference frequency. So this fix will end up being a software implementation on how we drive our PLL chip / command our frequency synthesizer. The good news, this technique works beautifully to remove integer-N boundary spurs. The datasheet lists the maximum PFD as 125 MHz. We stipulated in the previous paragraph that we wanted the PDF (reference frequency) to be above 100 MHz, so we have 25 MHz of freedom in the reference frequency that we can use to mitigate these integer-N boundary spurs.

Harmonics:

Okay, here is where we are going to have to settle a bit. Fractional PLL synthesizers tend out output a great deal of energy at harmonics of the fundamental they are outputting. So we'll need to set up a filter bank to deal with these harmonics the best we can. I will go through my work on that in the next material section.

The plot to the right is again an excerpt from the datasheet showing the power level of various harmonics relative to the carrier. You can see they're typically 30 dB ish lower in power. However, at low frequencies, the third and fifth harmonic can exceed the fundamental in power. This is something we will address specifically later.

Filter Bank Considerations

First I considered whether to make a parallel or cascaded filter bank. With the power of after-simulation knowledge as I write this, I am going to say I decided on a more traditional parallel filter bank. I was originally considering cascading my filters so that higher harmonics might reach cutoffs of some of the higher frequency filters and get extra attenuation. That worked a little bit, but what I saw more was that the gain at lower fundamental frequencies dropped due to the extra insertion loss from all the filters the signal had to go through.

I usually would never cascade filters so casually because typically their reactances would interact and you would be left with filters with behavior that doesn't match the datasheet. More specifically. If you put two filters together, because their reactances interact, you will not get the superposition of the two transfer functions of the filters. You will get something else that will be hard to determine and should probably be avoided or at least measured on a network analyzer.

HOWEVER, the XLF series filter from Mini-Circuits promises to be 50 ohms up to some high frequency like 20 or 30 GHz, and also specifically claims to be reflectionless and cascadable. I hadn't seen anything like that before, and figured no better time to try something wild than in a personal project. Fun food for thought. I may try this sometime, but for now, I am sticking with a parallel filter bank.

I did choose SPDT's as my primary type of switch for 2 reasons. COST, and COST. First of all, an SP4T or SP8T would be mega expensive. Second, even the low frequency terminals of the switch would be connected to a switch that has to be rated for higher frequencies. Hence the second cost. You'll notice most of my switches are the 4257-52 part number. These switches are about a buck as compared to the HMC1118LP3DETR which is well over $10. SP4T's started to approach $100.

You'll also notice I use a high frequency switch to multiplex which port of the PLL synthesizer goes through the filter bank. That's because port A only goes up to 6.8 GHz, and port B only goes from 6.8 GHz up to 13.6 GHz. The balun is required because port A is a differential output.

Lastly, and as a side note. The IP3 and 1dB compression points of these filters and switches are very high, around 35 to 60 dBm depending on the part. So I am not worried about non-linearities in this section of the design. Similarly, all of these parts are rated for far more power than the PLL synthesizer can put out, so we aren't going to be running anything too hot.

Scraping Plots

Okay, on to the cascade analysis of the cascaded filter bank. I started by installing plotDigitizer onto my computer with:

~$ pip3 install plotdigitizer

This tool let me scrape CSV data of all the insertion loss plots from all of the datasheets. First I preprocessed the screenshot of the plot with my own python script to adjust the colors of the trace, extra traces, background, and grid lines to make it easier for the plotDigitizer to read.

Then I cropped the image and ran it through the plotDigitizer. The tool provided me with a CSV file of frequency point in MHz and insertion loss in dB. Some points needed to be touched up manually, but for the most part, the tool worked great! The image to the right shows the original (preprocessed) plot taken right out of the datasheet, and the reconstructed plot from the set of data that was gathered. As you can see, they are quite identical!

I then read the CSV files into a python script and calculated what the cascaded gain would be given the frequency switch-points I chose to use.

Designing The Filter Bank

I had to make some trade-offs when deciding the frequency switch-points. My first pass at designing a filter bank had the cutoff frequency of successive filters two times higher than the cutoff frequency of a preceding filter. This would in theory enable me to have the second harmonic begin to be attenuated as soon as I move into the lowest frequency covered by a given filter in the bank. This wasn't great for 2 reasons. First, I needed LOTS of filters and switches. The sheer magnitude of switches the lower frequencies had to go through severely attenuated the lower frequencies. Not to mention the cost of all these parts. Second, in order to have the second harmonic really attenuated when the fundamental is set at the lowest frequency in the filters range, we'd have to accept that the fundamental itself would be severely attenuated at the highest frequency in the filters range. This could be fixed by adding in more filters and more switches with smaller ranges for each filter, but then we'd exacerbate the first problem of excess attenuation at lower frequencies.

Some sacrifice had to be made, so I took another look at the datasheet. In the datasheet for the PLL synthesizer (and image attached earlier) we see that the 2nd, and 4th harmonic stay about 25 to 35 dB below the carrier across the whole band. The 4th harmonic will be far out of our band of interest and attenuated much further due to the filters well past cutoff. The 2nd harmonic may not be at cutoff, but will at least get maybe 2 to 5 dB extra loss below what the datasheet specs. The 3rd and 5th harmonic are interesting. Roughly below 100 MHz, these signals are stronger than the carrier.

So my plan is this. I want to reduce the number of filter stages by 2 (1 is acceptable). I want to spread out the filters so that cutoff of one is between 2x and 3x the lowest frequency that filter will be used for. If I pick filters well, I can get about 20 to 30 dB of insertion loss at that 3rd harmonic, placing it at the signal strength of the others (20dB below the carrier). This acknowledges the harmonic issue and mitigates the ones that are the worst problem (3rd and 5th), and it improves the gain at low frequencies.

The real solution might be to avoid a fractional PLL synthesizer and get better signal purity from DDS, but I don't have $10K dollars to throw at this. I have $89.99. So there ya go.

The image to the right shows the cascaded gain of my filter bank using the scraped data we acquired in the previous section. I was able to pick filters such that the 3rd harmonic will be significantly attenuated. Each frequency range is larger than the ranges in my initial designs, and each frequency range should end at the filters 3dB cutoff point.

Finishing Up RF Synthesizer

After our RF signal goes through the filter bank, we will put it through the variable attenuator and amplifier to flatten the power level across frequency and boost it to the desired level. Then we will take that signal and route it through multiple switches (increased isolation) to select which way we send the RF signal through the DUT. All of this can be seen in the signal generator block diagram shown below.

Also, I went ahead and scrapped the info for the output power of the PLL from the datasheet and combined it with the gain of my filter bank. This plot is shown to the right. I used this information to determine how much attenuation was needed at any given frequency with the variable attenuator to flatten the power level.

LO Source

The LO source is very similar to the RF synthesizer. We use the same fractional PLL as we did for the RF synthesizer. The same filter bank. The same variable attenuator. The first difference is that we use two cascaded amplifiers instead of one to meet the mixer LO drive strength requirements. The second amplifier is the closest we come to hitting any non-linearities. We are no where near the output IP3 power of 26 dBm, but with an output power of 13 dBm, we are somewhat close to this amplifiers output P1dB (15 dBm). This could be problematic because we don't want other frequency content caused by non-linearities to mix down stuff in different bands down to our IF band. I think we will be okay because we have a few dB of margin on the P1dB, but if we are finding that we have a bit of trouble, I can always increase the attenuation on the variable attenuator. I purposely selected mixers in the receive chain that were spec'd over a range of LO drive strengths so I could be confident if I had to decrease the LO drive strength for any reason.

Receiver

My directional couplers will be off board from the main VNA unit, so I haven't designed them yet, but I am estimating from the paper I am reading about 16 dB of coupling bringing my input power level on the receive chain to about -20 dBm (max). So I start off my receive chain with an LNA. I wasn't able to find a mixer in my price range that covered the frequency range I needed, so I used an RF switch to switch between two mixers. One for lower frequencies. One for higher frequencies. I then pass the data through a 100 MHz cutoff low pass filter acting as my anti-aliasing filter (sampling at 200 MSPS). I pass my signal through a balun to feed my next op-amp (IF amplifier / differential). At this point, our signal strength is about -15 dBm (max). This does depend on frequency and conversion loss of the mixers, but all of this is detailed in the receive chain gain diagram to the right. The OP AMP I use has an open gain loop of 30 dB at 100 MHz, so I am going to set it's closed gain loop to 30 dB. That works out perfectly, because the output power of the OP AMP would be about 15 dBm. The signal level corresponding to the full scale voltage of the ADC (with a 50 ohm termination) is about 7.5 dBm. So we definitely can make use of the full scale of the ADC. We can either dial back the gain on our IF amp, or we can increase the attenuation on our variable attenuator. We'll probably work a combination of both so we are just about operating over the full scale when S21 is 0dB and the ports are tied together on this VNA.

I cannot afford to have four of these receive chains on the board, but sharing one receive chain among 4 RF channels will be problematic since the isolation of a typical switch just isn't spectacular. For that reason, I used extra switches so I could terminate each signal on its own switch before routing it to the switches that multiplex between signals. This should mitigate the isolation problem.

Also, you'll notice that for some frequencies the power level at the ADC is slightly above the full scale voltage. One, this is unlikely to happen in practice because of other unmodelled losses: SMA connectors, transmission line losses, cable losses. Two, we can always tune the attenuation at the variable attenuator in the RF synthesizer to ensure we make use of the full scale of the ADC without going over it's range / max-voltage.

Bunch of Electricals