Vector Network Analyzer (Schematic)

Overview

In this section, I'll be posting the pages of the schematic as I go. I'll generally post them as images so I can write something beside them, but when I make updates, I'll also update a PDF download at the bottom of this page because sometimes the images don't have the best resolution. Keep in mind, as long as this sentence is here, these are still being updated. A few of the schematic pages are missing a few small things I am going to work on later. For instance, the USB page doesn't contain the USB power monitor chip and 5V power supply that we need to provide as the host. This will be added in later. The POR reset line is a 12V push pull. This hasn't been routed to the FPGA because we need to do some level shifting on this signal while ensuring we don't introduce glitches. This will be added later. With that in mind, enjoy.

Schematic Pages

This is the top level diagram of my hierarchical schematic. It looks a lot like the block diagram with the FPGA connecting to all the other devices.

The ESP32 is the only device that will be programmed on this board. It will be responsible for configuring the FPGA through a parallel interface.

This USB chip connects to the FPGA over a 3.3V LVCMOS UTMI interface. It will act as a USB host for us to control an ECAL module if ever desired.

The ethernet controller will be a marvel chip operating over a 3.3V LVCMOS MII interface. This interface will send the measurement data to a screen.

Still incomplete. We have the mixers, RF switch, low pass filter (anti-alias) balun, IF AMP, and ADC. The ADC is run with a 200MHz LVPECL clock.

Differential OP AMP takes our -15 dBm signal and boost it to 2.73V across a 200 ohm load. This can barely overvoltage the ADC, but not destroy it.

Bunch of Electricals

Vector Network Analyzer (Schematic)

Overview

Schematic Pages

Schematic Download